Automatic Sleep Transistor Insertion
In nanoCMOS technologies, leakage power has become comparable to dynamic power
Leakage power minimization is now a design problem (and not just a technology/process problem) .
Capabilities :
1. Automatic gate clustering
2. Automatic peak current estimation
3. Automatic sleep transistor sizing
4. Support of different sleep transistor insertion strategies
5. Tight control of area and delay overhead
6. Automatic synthesis of sleep control logic
STI Flow
The graphical interface of
|
Reduces leakage power by automatic insertion of sleep transistor cells.
BullDAST s.r.l. - C.so Vinzaglio, 3 - 10121 Torino - ITALY