Complex digital circuits usually contain units that do not perform useful computations for some clock cycles. It is then possible to disable the logic when it is not in use in a particular clock cycle, with the objective of limiting power consumption. Clock gating provides a way to selectively stop the clock whenever the computation to be carried out by a hardware unit is redundant.

improves one of the major limitations of existing clock gating techniques: it takes advantage of situations when one part of a functional unit is in use while other parts are unused. 

uses more aggressive techniques for automatic clock gating extraction:

Capability of accounting for FFs which have explicit enable conditions.

High scalability to deal with large RTL circuits.

Minor and well controlled overhead in design speed and area.

In RTL design,detects non trivial redundant clocking by extracting a signal, from the logic description of the circuit, based on the observability conditions of the FFs to be isolated.