In  modern CMOS digital designs up to 40% of the total power dissipation is due to clock distribution: reducing clock net consumption  greatly impacts the overall design power budget.

is NOT a clock tree synthesis tool, it provides a set of constraints used to build a low power clock distribution network.

is based on an activity driven clock gating strategy applied to a placed design.

plans the clock tree structure by assigning to the same branch clocked elements with “close” activity which are also physically “close” in the placement. Power savings are obtained by masking off the clock, when not necessary, not only in the synchronous elements but also on the clock tree interconnections.

First, builds a clock tree topology balancing the reduction in clock switching against clock and activation function capacitive loading estimates. Then it inserts clock gating logic in the tree, balancing its power consumption against the power on the gatedclock sub-tree.The output of is not a layout of the clock tree, but a clock netlist which is fed to a back-end tool for clock routing.

The tool handles hierarchical placed designs in which synchronous modules can be identified.