Early power estimation is an essential requirement of any design flow. In the vast majority of cases, means "before synthesis", that is, before a synthesizable RTL description is fed to a synthesis tool to get a gate-level netlist. Such power estimation capability should be completely transparent to the existing synthesis flow.

is a power estimation engine that works with, and can be easily integrated to, many existing synthesis flows.

TOOL FEATURES

Most existing power estimation tools rely on low-effort synthesis to handle RTL descriptions. In other words, estimates are obtained through gate-level power analysis of a netlist that "approximates" the result of the actual synthesis. The availability of a fast synthesis engine is thus key for the success of tools adopting this estimation paradigm.

totally avoids synthesis; it performs power estimation by working on a mixed RT-gate level description obtained through source HDL analysis, elaboration and hardware inferencing.

Innovative power modeling capabilities allow the tool to handle HDL operators, memories and control as RTL design objects. Power models can be either pre-characterized, or built on-line. An effective caching mechanism enables easy model re-use to improve estimation efficiency.

supports the full VHDL/Verilog synthesizable subset.

The estimation flow of is depicted in the figure below.

USER INTERFACES

provides a user-friendly graphical interface that allows easy monitoring of design’s total power consumption, as well as quick identification of the most power-critical design objects. Detailed power figures can be dumped to file with different levels of verbosity for off-line analysis.

offers also a command-line interface that enables scripting, batch-mode execution and interfacing to existing design flows.

Modeling effort, estimation accuracy and synthesis constraints can be set by the user in both graphical and textual modes.

ACCURACY AND PERFORMANCE

is consistently more efficient, in terms of both accuracy and execution speed, than power estimation tools adopting the fast synthesis paradigm.

In design objects are annotated with real switching activities calculated through RTL simulation (as opposed to assuming a default switching activity for non-invariant objects). This dramatically helps in increasing estimation accuracy.

avoids both synthesis and gate-level simulation (usually, two very time-demanding tasks). This greatly contributes to the reduction of the total power estimation time.

achieves 30% accuracy with respect to gate-level estimates, with sensibly shorter execution times.